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ht49r10a-1/ht49c10-1 lcd type 8-bit mcu rev. 1.50 1 july 30, 2012 features operating voltage: f sys = 4mhz: 2.2v~5.5v f sys = 8mhz: 3.3v~5.5v 2 input lines 8 bidirectional i/o lines external interrupt input 8-bit programmable timer/event counter with pfd, programmable frequency divider, function lcd driver with 15 2, 15 3or14 4 segments 1k 14 program memory 64 8 data memory ram real time clock rtc rtc 8-bit prescaler watchdog timer buzzer output on-chip crystal, rc and 32768hz crystal oscillator power-down and wake-up feature reduce power con - sumption 2-level subroutine nesting bit manipulation instruction 14-bit table read instruction up to 0.5 s instruction cycle with 8mhz system clock 63 powerful instructions all instructions executed in 1 or 2 machine cycles low voltage reset/detector 44-pin qfp/lqfp package general description the ht49r10a-1 is an 8-bit, high performance, risc architecture microcontroller devices specifically de - signed for a wide range of lcd applications. the mask version ht49c10-1 is fully pin and functionally compati - ble with the otp version ht49r10a-1 device. the advantages of low power consumption, i/o flexibil - ity, programmable frequency divider, timer functions, oscillator options, power-down and wake-up functions and buzzer driver in addition to a flexible and configurable lcd interface, enhance the versatility of these devices to control a wide range of lcd-based ap - plication possibilities such as measuring scales, elec - tronic multimeters, gas meters, timers, calculators, remote controllers and many other lcd-based indus - trial and home appliance applications. technical document tools information faqs application note ha0017e controlling the read/write function of the ht24 series eeprom using the ht49 series mcus ha0024e using the rtc in the ht49 mcu series ha0025e using the time base in the ht49 mcu series ha0026e using the i/o ports on the ht49 mcu series ha0027e using the timer/event counter in the ht49 mcu series ha0075e mcu reset and oscillator circuits application note
block diagram pin assignment ht49r10a-1/ht49c10-1 rev. 1.50 2 july 30, 2012

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pad description pad name i/o options description pa0/bz pa1/bz pa2 pa3/pfd pa4~pa7 i/o wake-up pull-high or none cmos or nmos pa0~pa7 constitute an 8-bit bidirectional input/output port with schmitt trig - ger input capability. each pin on the port can be configured as a wake-up in - put by configuration options. pa0~pa3 can be configured as a cmos output or nmos input/output with or without pull-high resistor by configuration op - tions. pa4~pa7 are always pull-high nmos input/output. pa0~pa1 can be setup as i/o pins or buzzer outputs by a configuration option. pa3 can be setup as an i/o pin or as a pfd output also by a configuration option. pb0/int pb2/tmr i pb0 and pb2 constitute a 2-bit schmitt trigger input port. each pin on the port has a pull-high resistor. pb0 can be setup as an input pin or an external inter - rupt control pin (int ) by software application. pb2 can be setup as an input pin or as a timer/event counter input pin tmr also by software. vlcd i lcd power supply v1, v2, c1, c2 i voltage pump com0~com2 com3/seg14 o 1 / 2, 1 / 3or1 / 4 duty seg14 can be setup as a segment or as a common output driver for lcd panel by a configuration option. com0~com2 are the outputs for lcd panel. seg0~seg13 o lcd driver outputs for lcd panel segments osc1 osc2 i o crystal or rc osc1 and osc2 are connected to an rc network or a crystal, a configuration option for the internal system clock. in the case of rc opera - tion, osc2 is the output terminal for 1 / 4 system clock. the system clock may come from the rtc oscillator. if the system clock co - mes from rtc osc, these two pins can be left floating. osc3 osc4 i o rtc or system clock real time clock oscillators. osc3 and osc4 are connected to a 32768hz crystal oscillator for timing purposes or to a system clock source (depending upon the configuration options). vss negative power supply, ground vdd positive power supply res i schmitt trigger reset input, active low absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. ht49r10a-1/ht49c10-1 rev. 1.50 3 july 30, 2012
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage lvr disable, f sys =4mhz 2.2 5.5 v lvr disable, f sys =8mhz 3.3 5.5 v v lcd lcd power supply (note*) va 5.5v 2.2 5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz 12ma 5v 35ma i dd2 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz 48ma i dd3 operating current (f sys =rtc osc) 3v no load 0.3 0.6 ma 5v 0.6 1 ma i stb1 standby current (*f s =f sys /4) 3v no load, system halt, lcd off at halt 1 a 5v 2 a i stb2 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, c type 2.5 5.0 a 5v 10 20 a i stb3 standby current (*f s =wdt rc osc) 3v no load, system halt lcd on at halt, c type 25 a 5v 610 a i stb4 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias 17 30 a 5v 34 60 a i stb5 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias 13 25 a 5v 26 50 a i stb6 standby current (*f s =wdt rc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias 14 25 a 5v 28 50 a i stb7 standby current (*f s =wdt rc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias 10 20 a 5v 20 40 a v il1 input low voltage for i/o ports, tmr and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v i ol1 i/o port sink current 3v v ol =0.1v dd 612 ma 5v 10 25 ma i oh1 i/o port source current 3v v oh =0.9v dd 2 -4 ma 5v 5 8 ma i ol2 lcd common and segment current 3v v ol =0.1v dd 210 420 a 5v 350 700 a ht49r10a-1/ht49c10-1 rev. 1.50 4 july 30, 2012
symbol parameter test conditions min. typ. max. unit v dd conditions i oh2 lcd common and segment current 3v v oh =0.9v dd 80 160 a 5v 180 360 a r ph pull-high resistance 3v 20 60 100 k
5v 10 30 50 k
v lvr1 low voltage reset voltage lvr enable, 2.1v option 1.98 2.1 2.22 v v lvr2 lvr enable, 3.15v option 2.98 3.15 3.32 v v lvr3 lvr enable, 4.2v option 3.98 4.2 4.42 v v lvd1 low voltage detector voltage lvd enable, 2.2v option 2.08 2.2 2.32 v v lvd2 lvd enable, 3.3v option 3.12 3.3 3.50 v v lvd3 lvd enable, 4.4v option 4.12 4.4 4.70 v note: * for the value of va refer to the lcd driver section. *f s please refer to the wdt clock option a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc, rc osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (32768hz crystal osc) 32768 hz f rtcosc rtc frequency 32768 hz f timer timer i/p frequency 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 *t sys t lvr low voltage width to reset 0.25 1 2 ms t int interrupt pulse width 1 s note: *t sys = 1/f sys1 or 1/f sys2 ht49r10a-1/ht49c10-1 rev. 1.50 5 july 30, 2012
power-on reset characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms ht49r10a-1/ht49c10-1 rev. 1.50 6 july 30, 2012
ht49r10a-1/ht49c10-1 rev. 1.50 7 july 30, 2012 functional description execution flow the system clock is derived from either a crystal or an rc oscillator or a 32768hz crystal oscillator. it is inter - nally divided into four non-overlapping clocks. one in - struction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. the pipelining scheme causes each instruction to effec - tively execute in a cycle. if an instruction changes the value of the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) is of 10 bits wide and controls the sequence in which the instructions stored in the pro - gram rom are executed. the contents of the pc can specify a maximum of 1024 addresses. after accessing a program memory word to fetch an in - struction code, the value of the pc is incremented by one. the pc then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading a pcl register, a subroutine call, an ini - tial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth - erwise proceed with the next instruction. the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl per - forms a short jump. the destination is within 256 loca - tions. when a control transfer takes place, an additional dummy cycle is required. / & ( ! ( 9 : ; ( ! ( 9 < : / & ( ! ( 9 = : ; ( ! ( 9 : / & ( ! ( 9 = : ; ( ! ( 9 = : = = ( > ? ( 9 (
> : execution flow mode program counter *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000 external interrupt 0000000100 timer/event counter overflow 0000001000 time base interrupt 0000001100 rtc interrupt 0000010000 skip program counter + 2 loading pcl *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *9~*0: program counter bits s9~s0: stack register bits #9~#0: instruction code bits @7~@0: pcl bits
ht49r10a-1/ht49c10-1 rev. 1.50 8 july 30, 2012 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 1024 14 bits which are addressed by the program counter and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialization. after chip reset, the program always begins execution at this location. location 004h location 004h is reserved for the external interrupt service program. if the int input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the timer/event counter interrupt service program. if a timer interrupt results from a timer/event counter overflow, and if the inter - rupt is enabled and the stack is not full, the program begins execution at location 008h. location 00ch location 00ch is reserved for the time base interrupt service program. if a time base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 00ch. location 010h location 010h is reserved for the real time clock inter- rupt service program. if a real time clock interrupt oc- curs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 010h. table location any location in the rom can be used as a look-up ta - ble. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to tblh (table higher-order byte register) (08h). only the destination of the lower-order byte in the table is well-defined; the other bits of the ta - ble word are all transferred to the lower portion of tblh, and the remaining 2 bit is read as 0 . the tblh is read only, and the table pointer (tblp) is a read/write register (07h), indicating the table location. before accessing the table, the location should be placed in tblp. all the table related instructions re - quire 2 cycles to complete the operation. these areas may function as a normal rom depending upon the user s requirements. stack register stack the stack register is a special part of the memory used to save the contents of the program counter. the stack is organized into 2 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. its activated level is indexed by a stack pointer (sp) and is neither readable nor writeable. at a commencement of a subroutine call or an interrupt ac- knowledgment, the contents of the program counter is pushed onto the stack. at the end of the subroutine or in- terrupt routine, signaled by a return instruction (ret or reti), the contents of the program counter is restored to its previous value from the stack. after chip reset, the stack pointer will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the ac - knowledgment is still inhibited. once the stack pointer is decremented (by ret or reti), the interrupt is ser - viced. this feature prevents stack overflow, allowing the programmer to use the structure easily. likewise, if the stack is full, and a call is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent two return addresses are stored). / / 4
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ht49r10a-1/ht49c10-1 rev. 1.50 9 july 30, 2012 data memory ram the data memory (ram) is designed with 79 8 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. of the two types of functional groups, the special func - tion registers consist of an indirect addressing register 0 (00h), a memory pointer register 0 (mp0;01h), an indi - rect addressing register 1 (02h), a memory pointer reg - ister 1 (mp1;03h), a bank pointer (bp;04h), an accumulator (acc;05h), a program counter lower-order byte register (pcl;06h), a t able pointer (tblp;07h), a table higher-order byte register (tblh;08h), a real time clock control register (rtcc;09h), a status register (status;0ah), an inter - rupt control register 0 (intc0;0bh), a timer/event coun - ter (tmr;0dh), a timer/event counter control register (tmrc;0eh), i/o registers (pa;12h, pb;14h), and in - terrupt control register 1 (intc1;1eh). on the other hand, the general purpose data memory, addressed from 40h to 7fh, is used for data and control informa - tion under instruction commands. the areas in the ram can directly handle arithmetic, logic, increment, decrement, and rotate operations. ex - cept some dedicated bits, each pin in the ram can be set and reset by set [m].i and clr [m].i they are also indirectly accessible through the memory pointer register 0 (mp0;01h) or the memory pointer register 1 (mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1(03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 (7-bit) and mp1 (7-bit), used to access the ram by combining corresponding indirect address - ing registers. mp0 can only be applied to data memory, while mp1 can be applied to data memory and lcd dis - play memory. accumulator acc the accumulator (acc) is related to the alu opera - tions. it is also mapped to location 05h of the ram and is capable of operating with immediate data. the data movement between two data memory locations must pass through the acc. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz etc.) the alu not only saves the results of a data operation but also changes the status register. > ( ( ) ) 4 ) 4 ) 4 ) 4 ) 4 ) 5 4 ) 6 4 ) 1 4 ) 7 4 ) 8 4 ) $ 4 ) + 4 ) 4 ) 4 ) 4 ) / 4 ) 4 4 4 4 4 5 4 6 4 1 4 7 4 8 4 $ 4 + 4 4 4 4 / 4 1 / 4 a ( "
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ht49r10a-1/ht49c10-1 rev. 1.50 10 july 30, 2012 status register status the status register (0ah) is of 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. except the to and pdf flags, bits in the status regis - ter can be altered by instructions similar to other regis - ters. data written into the status register does not alter the to or pdf flags. operations related to the status register, however, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clear - ing the watchdog timer and executing the halt in - struction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing the subroutine call, the status register will not be automati - cally pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. interrupts the device provides an external interrupt, an internal timer/event counter interrupt, an internal time base in- terrupt, and an internal real time clock interrupt. the in- terrupt control register 0 (intc0;0bh) and interrupt control register 1 (intc1;1eh) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. once an interrupt subroutine is serviced, other inter- rupts are all blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 or of intc1 may be set in order to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is en - abled, until the sp is decremented. if immediate service is desired, the stack should be prevented from becom - ing full. all these interrupts provide a wake-up function. as an in - terrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack fol - lowed by a branch to a subroutine at the specified loca - tion in the program memory. only the contents of the program counter is pushed onto the stack. if the con - tents of the register or of the status register (status) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. external interrupts are triggered by a high to low transi - tion of int , and the related interrupt request flag (eif;bit 4 of intc0) is set as well. after the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04h occurs. the interrupt re - quest flag (eif) and emi bits are all cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf;bit 5 of intc0), which is normally caused by a timer overflow. after the interrupt is enabled, and the stack is not full, and the tf bit is set, a subroutine call to location 08h occurs. the related interrupt request flag (tf) is re- set, and the emi bit is cleared to disable further inter- rupts. the time base interrupt is initialized by setting the time base interrupt request flag (tbf;bit 6 of intc0), that is caused by a regular time base signal. after the interrupt bit no. label function 0c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register
ht49r10a-1/ht49c10-1 rev. 1.50 11 july 30, 2012 is enabled, and the stack is not full, and the tbf bit is set, a subroutine call to location 0ch occurs. the re - lated interrupt request flag (tbf) is reset and the emi bit is cleared to disable further interrupts. the real time clock interrupt is initialized by setting the real time clock interrupt request flag (rtf;bit 4 of intc1), that is caused by a regular real time clock sig- nal. after the interrupt is enabled, and the stack is not full, and the rtf bit is set, a subroutine call to location 10h occurs. the related interrupt request flag (rtf) is reset and the emi bit is cleared to disable further inter- rupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are all held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set both to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti sets the emi bit and en - ables an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses are serviced on the latter of the two t2 pulses if the corresponding interrupts are enabled. in the case of simultaneous requests, the priorities in the following table apply. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter overflow 2 08h time base interrupt 3 0ch real time clock interrupt 4 10h the timer/event counter interrupt request flag (tf), ex - ternal interrupt request flag (eif) , time base interrupt request flag (tbf), enable timer/event counter inter- rupt bit (eti), enable external interrupt bit (eei) , enable time base interrupt bit (etbi), and enable master inter- rupt bit (emi) make up of interrupt control register 0 (intc0) which is located at 0bh in the ram. the real time clock interrupt request flag (rtf) and enable real time clock interrupt bit (erti) on the other hand, consti- tute the interrupt control register 1 (intc1) which is lo- cated at 1eh in the ram. emi, eei, eti, etbi and erti are all used to control the enable/disable status of inter - rupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (tbf, rtf, tf and eif) are all set, they remain in the intc0 or intc1 respectively until the interrupts are serviced or cleared by a software instruction. it is recommended that programs do not use a call subroutine within the interrupt subroutine. this is be - cause interrupts often occur in an unpredictable manner or require to be serviced immediately in some applica - tions. at this time, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original con - trol sequence. bit no. label function 0 emi control the master (global) interrupt (1=enabled; 0=disabled) 1 eei control the external interrupt (1=enabled; 0=disabled) 2 eti control the timer/event counter interrupt (1=enabled; 0=disabled) 3 etbi control the time base interrupt (1=enabled; 0:disabled) 4 eif external interrupt request flag (1=active; 0=inactive) 5 tf internal timer/event counter request flag (1=active; 0=inactive) 6 tbf time base request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc0 (0bh) register bit no. label function 0 erti control the real time clock interrupt (1=enabled; 0:disabled) 1~3, 5~7 unused bit, read as 0 4 rtf real time clock request flag (1=active; 0=inactive) intc1 (1eh) register
ht49r10a-1/ht49c10-1 rev. 1.50 12 july 30, 2012 oscillator configuration the device provides three oscillator circuits for system clocks, i.e., rc oscillator, crystal oscillator and 32768hz crystal oscillator, determined by configuration options. no matter what type of oscillator is selected, the signal is used for the system clock. the halt mode stops the sys - tem oscillator (rc and crystal oscillator only) and ignores external signals to conserve power. the 32768hz crystal oscillator (system oscillator) still runs when in the halt mode. if the 32768hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. since the 32768hz oscillator is also designed for timing purposes, the inter - nal timing (rtc, time base, wdt) operation still runs even if the system enters the halt mode. of the three oscillators, if the rc oscillator is used, an external resistor between osc1 and vss is required, and the range of the resistance should be from 24k
to 1m
. the system clock, divided by 4, is available on osc2 with a pull-high resistor, which can be used to synchronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temperature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accu - rate oscillator frequency is desired. if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other ex- ternal components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two exter- nal capacitors on osc1 and osc2 are required. there is another oscillator circuit designed for the real time clock. in this case, only the 32.768khz crystal oscil - lator can be applied. the crystal should be connected between osc3 and osc4. the rtc oscillator circuit can be controlled to start up quickly by setting the qosc bit (bit 4 of rtcc). it is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. although the system enters the power down mode, the system clock stops, and the wdt oscillator still works with a pe - riod of approximately 65 s at 5v. the wdt oscillator can be disabled by configuration options to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (rtc oscillator). the timer is designed to prevent a software malfunction or se - quence from jumping to an unknown location with unpre - dictable results. the wdt can be disabled by configuration options. but if the wdt is disabled, all exe - cutions related to the wdt lead to no operation. the wdt time-out period is f s /2 15 ~f s /2 16 . if the wdt clock source chooses the internal wdt oscillator, the time-out period may vary with temperature, vdd, and process variations. if the clock source selects the instruc- tion clock and the halt instruction is executed, the wdt may stop counting and lose its protecting purpose, and the logic can only be restarted by external logic. > ( > > ( > > ' - * 1 6 7 4 b ( > * ( > > 1 ) / system oscillator symbol parameter min. typ. max. unit f o nominal frequency 32.768 khz esr series resistance 50 65 k
c l load capacitance 9 pf note: 1. it is strongly recommended to use a crystal with load capacitance 9pf. 2. the oscillator selection can be optimized using a high quality resonator with small esr value. refer to crystal manufacturer for more details: www.microcrystal.com crystal specifications
ht49r10a-1/ht49c10-1 rev. 1.50 13 july 30, 2012 when the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt instruction will stop the system clock. the wdt overflow under normal operation initializes a chip reset and sets the status bit to . in the halt mode, the overflow initializes a warm reset , and only the program counter and stack pointer are reset to zero. to clear the contents of the wdt, there are three meth - ods to be adopted, i.e., external reset (a low level to res ), software instruction, and a halt instruction. there are two types of software instructions; clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one type of instruction can be active at a time depending on the options clr wdt times selection option. if the clr wdt is selected (i.e., clr wdt times equal one), any execution of the clr wdt instruction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e., clr wdt times equal two), these two instructions have to be executed to clear the wdt; otherwise, the wdt may reset the chip due to a time-out. multi-function timer the device provides a multi-function timer for the wdt, time base and rtc but with different time-out periods. the multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the wdt osc or rtc osc or the instruction clock (i.e., system clock divided by 4). the multi-function timer also provides a selectable frequency signal (ranges from f s /2 2 to f s /2 8 ) for lcd driver circuits, and a selectable fre - quency signal (ranges from f s /2 2 to f s /2 9 ) for the buzzer output by configuration options. it is recommended to select a frequency as new as possible to 4khz for the lcd driver circuits for a proper display. time base the time base offers a periodic time-out period to gener - ate a regular internal interrupt. its time-out period ranges from f s /2 12 to f s /2 15 selected by a configuration option. if a time base time-out occurs, the related inter - rupt request flag (tbf; bit 6 of intc0) is set. if the inter - rupt is enabled, and the stack is not full, a subroutine call to location 0ch occurs. real time clock rtc the real time clock (rtc) is operated in the same manner as the time base that is used to supply a regular internal interrupt. its time-out period ranges from f s /2 8 to f s /2 15 by software programming . writing data to rt2, rt1 and rt0 (bit2, 1, 0 of rtcc;09h) yields various ( ( ( ( ( ( ( ( ' ( + (
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ht49r10a-1/ht49c10-1 rev. 1.50 14 july 30, 2012 time-out periods. if an rtc time-out occurs, the related interrupt request flag (rtf; bit 4 of intc1) is set. but if the interrupt is enabled, and the stack is not full, a subroutine call to location 10h occurs. the real time clock time-out signal also can be applied to be a clock source for the timer/event counter to obtain longer time-out periods. rt2 rt1 rt0 rtc clock divided factor 000 2 8 * 001 2 9 * 010 2 10 * 011 2 11 * 100 2 12 101 2 13 110 2 14 111 2 15 note: * not recommended for use. power down operation halt the halt mode is initialized by the halt instruction and results in the following. the system oscillator turns off but the wdt or rtc oscillator keeps running (if the wdt oscillator or the real time clock is selected). the contents of the on-chip ram and of the registers remain unchanged. the wdt is cleared and start recounting (if the wdt clock source is from the wdt oscillator or the real time clock oscillator). all i/o ports maintain their original status. the pdf flag is set but the to flag is cleared. lcd driver is still running (if the wdt osc or rtc osc is selected). the system quits the halt mode by an external reset, an interrupt, an external falling edge signal on port a, or a wdt overflow. an external reset causes device initial - ization, and the wdt overflow performs a warm reset . after examining the to and pdf flags, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or by executing the clr wdt instruction, and is set by executing the halt instruction. on the other hand, the to flag is set if wdt time-out occurs, and causes a wake-up that only resets the program counter and sp, and leaves the others at their original state. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each pin in port a can be independently selected to wake up the device by configuration options. awakening from an i/o port stimulus, the program resumes execution of the next instruction. on awakening from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the pro - gram resumes execution at the next instruction. but if the interrupt is enabled, and the stack is not full, the reg - ular interrupt response takes place. when an interrupt request flag is set before entering the halt status, the system cannot be awaken using that interrupt. if a wake-up event occurs, it takes 1024 t sys (system clock periods) to resume normal operation. in other words, a dummy period is inserted after the wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, the execution will be per - formed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which reset may occur. res is reset during normal operation res is reset during halt wdt time-out is reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and sp and leaves the other circuits at their original state. some registers re- main unaffected during any other reset conditions. most registers are reset to the initial condition once the re- set conditions are met. examining the pdf and to flags, the program can distinguish between different chip resets. note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference. to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem awakes from the halt state. awaking from the halt state, the sst delay is added. an extra option load time delay is added during reset and power on.
ht49r10a-1/ht49c10-1 rev. 1.50 15 july 30, 2012 the states of the registers are summarized below: register reset (power on) wdt time-out (norma operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- program counter 0000h 0000h 0000h 0000h 0000h mp0 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu mp1 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u rtcc --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb ---- -r-r ---- -r-r ---- -r-r ---- -r-r ---- -r-r note: * stands for warm reset u stands for unchanged x stands for unknown - stands for unimplemented r stands for pb input bit 0 and bit 2 are read only the functional unit chip reset status is shown below. program counter 000h interrupt disabled prescaler, divider cleared wdt, rtc, time base cleared. after master reset, wdt starts counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack . 4 $ % . < ;
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ht49r10a-1/ht49c10-1 rev. 1.50 16 july 30, 2012 timer/event counter one timer/event counters is implemented in the device. it contains an 8-bit programmable count-up counter. the timer/event counter clock source may come from the system clock or system clock/4 or rtc time-out sig - nal or external source. system clock source or system clock/4 is selected by configuration options. using ex - ternal clock input allows the user to count external events, measure time internals or pulse widths, or gen - erate an accurate time base. while using the internal clock allows the user to generate an accurate time base. there are two registers related to the timer/event coun - ter, i.e., tmr ([0dh]) and tmrc ([0eh]). there are also two physical registers which are mapped to tmr loca - tion; writing tmr places the starting value in the timer/event counter preload register, while reading it yields the contents of the timer/event counter. tmrc is a timer/event counter control register used to define some options. the tm0 and tm1 bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external tmr pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal tmr, and the counting is based on the internal selected clock source. in the event count or timer mode, the timer/event coun- ter starts counting at the current contents in the timer/event counter and ends at ffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re- quest flag (tf; bit 5 of intc0). in the pulse width measurement mode with the va lues of the ton and te bits equal to one, after the tmr has received a transient from low to high (or high to low if the te bit is 0 ), it will start counting until the tmr returns to the original level and resets the ton. the measured result remains in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be made until the ton is set. the cycle measurement will re-function as long as it receives further transient pulse. in this oper - ation mode, the timer/event counter begins counting ac - cording not to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton is automatically cleared after the measurement cycle is completed. but in the other two modes, the ton can only be reset by in - structions. the overflow of the timer/event counter is one of the wake-up sources and can also be applied to a pfd (programmable frequency divider) output at pa3 by configuration options. no matter what the operation mode is, writin ga0toeti disables the related interrupt service. when the pfd function is selected, executing clr [pa].3 instruction to enable pfd output and execut - ing set [pa].3 instruction to disable pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re- loads that data to the timer/event counter. but if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event coun- ter preload register. the timer/event counter still contin- ues its operation until an overflow occurs. when the timer/event counter (reading tmr) is read, the clock is blocked to avoid errors. as this may results in a counting error, blocking of the clock should be taken into account by the programmer. it is strongly recommended to load a desired value into the tmr register first, then turn on the related timer/event counter for proper operation, because the initial value of tmr is unknown. ( > ? ) ) ! > ( . &
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ht49r10a-1/ht49c10-1 rev. 1.50 17 july 30, 2012 bit no. label function 0~2 unused bit, read as 0 3te defines the tmr active edge of the timer/event counter: in event counter mode (tm1,tm0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (tm1,tm0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 ton to enable/disable timer counting (0=disabled; 1=enabled) 5ts 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0=rtc outputs; 1= system clock or system clock/4) 6 7 tm0 tm1 to define the operating mode (tm1, tm0) 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmrc (0eh) register due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredict - able result. after this procedure, the timer/event function can be operated normally. input/output ports there are an 8-bit bidirectional input/output port and a 2-bit input port in the device, labeled pa, pb which are mapped to [12h], [14h] of the ram, respectively. pa0~pa3 can be configured as cmos (output) or nmos (input/output) with or without pull-high resistor by configuration options. pa4~pa7 always have pull-high re- sistors and are nmos (input/output). if nmos (input) is chosen, each pin on the port (pa0~pa7) can be configured as a wake-up input. pb can only be used for input operation. all the ports for the input operation (pa, pb), are non-latched, that is, the in - puts should be ready at the t2 rising edge of the instruc - tion mov a, [m] (m=12h or 14h). for pa output operation, all data is latched and remains unchanged until the output latch is rewritten. when the pa structures are open drain nmos type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the nmos device. that is executing first the instruction set [m].i (i=0~7 for pa) to disable the related nmos device, and then executing a mov a, [m] to get stable data. after a chip reset, these input lines remain at a high level or are left floating (by configuration options). each pin of these output latches can be set or cleared by the mov [m], a (m=12h) instruction. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i, cpl [m], cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. when a pa line is used as an i/o line, the related pa line options should be config- ured as nmos with or without pull-high resistor. once a pa line is selected as a cmos output, the i/o function cannot be used. the input state of a pa line is read from the related pa pad. when pa is configured as nmos with or without pull-high resistors, one should be careful when applying a read-modify-write instruction to pa. since the read-mod - ify-write will read the entire port state (pads state) firstly, execute the specified instruction and then write the result to the port data register. when the read operation is exe - cuted, a fault pad state (caused by the load effect or float - ing state) may be read. errors will then occur. there are three function pins that share with the pa port: pa0/bz, pa1/bz and pa3/pfd. the bz and bz are buzzer driving output pair and the pfd is a programmable frequency divider output. if the user wants to use the bz/bz or pfd function, the related pa port should be set as a cmos output. the buzzer output signals are controlled by pa0 and pa1 data regis - ters as defined in the following table. pa1 data register pa0 data register pa0/pa1 pad state 0 0 pa0=bz, pa1=bz 1 0 pa0=bz, pa1=0 x 1 pa0=0, pa1=0 note: x stands for unused
ht49r10a-1/ht49c10-1 rev. 1.50 18 july 30, 2012 the pfd output signal function is controlled by the pa3 data register and the timer/event counter state. the pfd output signal frequency is also dependent on the timer/event counter overflow period. the definitions of pfd control signal and pfd output frequency are listed in the following table. timer timer preload value pa3 data register pa3 pad state pfd frequency off x 0 u x off x 1 0 x on n 0 pfd f int /[2(256n)] on n 1 0 x note: x stands for unused u stands for unknown ( + ( . ? > > < + ) + pb input port " # . ? < (
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ht49r10a-1/ht49c10-1 rev. 1.50 19 july 30, 2012 lcd display memory the device provides an area of embedded data memory for lcd display. this area is located from 40h to 4eh of the ram at bank 1. bank pointer (bp; located at 04h of the ram) is the switch between the ram and the lcd display memory. when the bp is set as 01h , any data written into 40h~4eh will effect the lcd display. when the bp is cleared to 00h , any data written into 40h~4eh means to access the general purpose data memory. the lcd display memory can be read and writ - ten to only by indirect addressing mode using mp1. when data is written into the display data area, it is auto - matically read by the lcd driver which then generates the corresponding lcd driving signals. to turn the dis - play on or off, a 1 or a 0 is written to the correspond - ing bit of the display memory, respectively. the figure illustrates the mapping between the display memory and lcd pattern for the device. lcd driver output the output number of the lcd driver device can be 15 2, 15 3or14 4 by configuration option (i.e., 1 / 2 duty, 1 / 3 duty or 1/4 duty). the bias type lcd driver can be r type or c type by configuration option. if the r bias type is selected, no external capacitor is required. if the c bias type is selected, a capacitor mounted be - tween c1 and c2 pins is needed. there are two types of lcd bias power can be selected by configuration op - ! " # ) g g ( $ + ( ( ( $ > > ( ( % ( 3 ( ( ) ( ( $ ! ) g g h ( $ > > ( ( % ( 3 ( ( $ + ( $ + ( ( ( $ + ( $ + ( ( ( $ + ( $ + ( ( ( $ + ( $ + ( ( ( $ + ( ( $ + ( ( $ + ( ( $ + ( ( $ + ( ( $ + ( % (
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ht49r10a-1/ht49c10-1 rev. 1.50 21 july 30, 2012 configuration options the following shows the configuration options in the device. all these options should be defined in order to ensure proper functioning system. options osc type selection. this option is to determine whether an rc or crystal or 32768hz crystal oscillator is chosen as the system clock. wdt clock source selection. rtc and time base. there are three types of selection: system clock/4 or rtc osc or wdt osc. wdt enable/disable selection. wdt can be enabled or disabled by configuration options. clr wdt times selection. this option defines how to clear the wdt by instruction. one time means that the clr wdt can clear the wdt. two times means that if both of the clr wdt1 and clr wdt2 have been executed, only then will the wdt be cleared. time base time-out period selection. the time base time-out period ranges from clock/2 12 to clock/2 15 clock means the clock source selected by configuration option. buzzer output frequency selection. there are eight types of frequency signals for the buzzer output: clock/2 2 ~clock/2 9 . clock means the clock source selected by configuration option. wake-up selection. this option defines the wake-up capability. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge. pull-high selection. this option is to decide whether the pull-high resistance is visible or not on pa0~pa3. (pb and pa4~pa7 are always pull-high) pa0~pa3 cmos or nmos selection. the structure of pa0~pa3 4 bits can be selected as cmos or nmos individually. when the cmos is selected, the related pins only can be used for output operations. when the nmos is selected, the related pins can be used for input or output operations. (pa4~pa7 are always nmos) clock source selection of timer/event counter. there are two types of selection: system clock or system clock/4. i/o pins share with other functions selection. pa0/bz , pa1/bz: pa0 and pa1 can be set as i/o pins or buzzer outputs. pa3/pfd: pa3 can be set as i/o pins or pfd output. lcd common selection. there are three types of selection: 2 common (1 / 2 duty) or 3 common (1 / 3 duty) or 4 common (1 / 4 duty). if the 4 common is selected, the segment output pin seg14 will be set as a common output. lcd bias power supply selection. there are two types of selection: 1 / 2 bias or 1 / 3 bias lcd bias type selection. this configuration option is to determine what kind of bias is selected, r type or c type. lcd driver clock selection. there are seven types of frequency signals for the lcd driver circuits: f s /2 2 ~f s /2 8 . f s means the clock source selection by configuration option. lcd on/off at halt selection. lvr selection. lvr has an enable or disable option. lvd selection. lvd has an enable or disable option. lvd/lvr voltage selection. there are three levels of selection: 2.2v/2.1v, 3.3v/3.15v or 4.4v/4.2v
application circuits note: 1. crystal/resonator system oscillators for crystal oscillators, c1 and c2 are only required for some crystal frequencies to ensure oscillation. for resonator applications c1 and c2 are normally required for oscillation to occur. for most applications it is not necessary to add r1. however if the lvr function is disabled, and if it is required to stop the oscillator when v dd falls below its operating range, it is recommended that r1 is added. the values of c1 and c2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. reset circuit the reset circuit resistance and capacitance values should be chosen to ensure that vdd is stable and re - mains within its operating voltage range before the res pin reaches a high level. ensure that the length of the wiring connected to the res pin is kept as short as possible, to avoid noise interference. 3. for applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to application note ha0075e for more information. ht49r10a-1/ht49c10-1 rev. 1.50 22 july 30, 2012 1 6 7 4 b ) / ' - * 1 ) / % & & ' % ? j j ( ) * + , - ' & ' % (
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ht49r10a-1/ht49c10-1 rev. 1.50 23 july 30, 2012 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht49r10a-1/ht49c10-1 rev. 1.50 24 july 30, 2012 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht49r10a-1/ht49c10-1 rev. 1.50 25 july 30, 2012 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht49r10a-1/ht49c10-1 rev. 1.50 26 july 30, 2012
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht49r10a-1/ht49c10-1 rev. 1.50 27 july 30, 2012
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht49r10a-1/ht49c10-1 rev. 1.50 28 july 30, 2012
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht49r10a-1/ht49c10-1 rev. 1.50 29 july 30, 2012
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht49r10a-1/ht49c10-1 rev. 1.50 30 july 30, 2012
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht49r10a-1/ht49c10-1 rev. 1.50 31 july 30, 2012
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht49r10a-1/ht49c10-1 rev. 1.50 32 july 30, 2012
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht49r10a-1/ht49c10-1 rev. 1.50 33 july 30, 2012
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht49r10a-1/ht49c10-1 rev. 1.50 34 july 30, 2012
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht49r10a-1/ht49c10-1 rev. 1.50 35 july 30, 2012
package information note that the package information provided here is for consultation purposes only. as this information may be updated at regu - lar intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 0.528 b 0.390 0.398 c 0.512 0.528 d 0.390 0.398 e 0.031 f 0.012 g 0.075 0.087 h 0.106 i 0.010 0.020 j 0.029 0.037 k 0.004 0.008 l 0.004 07 symbol dimensions in mm min. nom. max. a 13.00 13.40 b 9.90 10.10 c 13.00 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.25 0.50 j 0.73 0.93 k 0.10 0.20 l 0.10 07 ht49r10a-1/ht49c10-1 rev. 1.50 36 july 30, 2012 $ + / 4 k 2 %
44-pin lqfp (10mm 10mm) (fp3.2mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 0.520 0.528 b 0.390 0.394 0.398 c 0.512 0.520 0.528 d 0.390 0.394 0.398 e 0.031 f 0.012 g 0.053 0.055 0.057 h 0.063 i 0.004 0.010 j 0.041 0.047 0.053 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 13.00 13.20 13.40 b 9.90 10.00 10.10 c 13.00 13.20 13.40 d 9.90 10.00 10.10 e 0.80 f 0.30 g 1.35 1.40 1.45 h 1.60 i 0.10 0.25 j 1.05 1.20 1.35 k 0.10 0.25 07 ht49r10a-1/ht49c10-1 rev. 1.50 37 july 30, 2012 $ + / 4 k 2
ht49r10a-1/ht49c10-1 rev. 1.50 38 july 30, 2012 copyright 2012 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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